During the production (e.g., fabrication, generation, manufacture, etc.) of a heterostructure device, selective etching of one or more layers in the heterostructure device is frequently performed. In general, selective etching removes some or all of a layer of a first material while removing little or none of an adjacent layer of a second material. Using selective etching, layers in the heterostructure device can be configured to form a desired pattern, e.g., partially cover another layer, have a varying thickness, and/or the like.
For example, selective etching can be used to form a recessed gate in a Heterostructure Field Effect Transistor (HFET), such as a Gallium Nitride (GaN)-based HFET. Inclusion of the recessed gate in the GaN-based HFET can increase the breakdown voltage, alleviate non-ideal effects, suppress current instabilities, and/or the like. To date, selective etching approaches rely on the difference between the etching rates for GaN and Aluminum Nitride (AlN) layers. In particular, two etching technologies are currently used to generate recessed gates in AlGaN/GaN HFETs, reactive ion etching (RIE) and chemical (wet) etching under deep Ultraviolet (UV).
However, use of either technology has its drawbacks. For example, the RIE approach damages the two-dimensional electron gas and significantly decreases the HFET saturation current, while the chemical etching approach is slow, making it difficult to achieve a desired etching pattern. Further, neither approach provides a solution for the selective etching of AlN layers, which are widely used in nitride-based electronic and optoelectronic devices.
In view of the foregoing, there exists a need in the art to overcome one or more of the deficiencies indicated herein and/or one or more other deficiencies not expressly discussed herein.